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18-bit, 1.25 msps pulsar ? adc ad7643 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006 analog devices, inc. all rights reserved. features throughput: 1.25 msps inl: 1.5 lsb typical, 3 lsb maximum (11 ppm of full scale) 18-bit resolution with no missing codes dynamic range: 95 db typical sinad: 93.5 db typical @ 20 khz (v ref = 2.5 v) thd: ?113 db typical @ 20 khz (v ref = 2.5 v) 2.048 v internal reference: typical drift 8 ppm/c; temp output differential input range: v ref (v ref up to 2.5 v) no pipeline delay (sar architecture) parallel (18-, 16-, or 8-bit bus) and serial 5 v/3.3 v/2.5 v interface spi?/qspi?/microwire?/dsp compatible single 2.5 v supply operation power dissipation 65 mw typical @ 1.25 msps with internal ref 2 w in power-down mode pb-free, 48-lead lqfp and 48-lead lfcsp_vq pin compatible with the ad7641 and other pulsar adcs applications medical instruments high speed data acquisition/high dynamic data acquisition digital signal processing spectrum analysis instrumentation communications ate general description the ad7643 is an 18-bit, 1.25 msps, charge redistribution sar, fully differential, analog-to-digital converter (adc) that operates from a single 2.5 v power supply. the part contains a high speed, 18-bit sampling adc, an internal conversion clock, an internal reference (and buffer), error correction circuits, and both serial and parallel system interface ports. the part has no latency and can be used in asynchronous rate applications. the ad7643 is hardware factory calibrated and tested to ensure ac parameters, such as signal-to-nois e ratio (snr), in addition to the more traditional dc parameters of gain, offset, and linearity. the ad7643 is only available in pb-free packages with operation specified from ?40c to +85c. functional block diagram 18 control logic and calibration circuitry clock ad7643 dgnd dvdd avdd agnd ref refgnd in+ in? pd reset pdbuf refbufin pdref ref temp d[17:0] busy rd cs d0/ob/2c ognd ovdd mode1 mode0 ref amp cnvst serial port parallel interface switched cap dac 06024-001 figure 1. table 1. pulsar 48-lead selection type/ksps 100 to 250 500 to 570 650 to 1000 >1000 pseudo differential ad7651 , ad7660 , ad7661 ad7650 , ad7652, ad7664 , ad7666 ad7653 , ad7667 true bipolar ad7610 , ad7663 ad7665 ad7612 , ad7671 true differential ad7675 ad7676 ad7677 ad7621 , ad7622, ad7623 18-bit multichannel/ ad7631 , ad7678 ad7679 ad7634 , ad7674 ad7641 , ad7643 simultaneous ad7654 ad7655 product highlights 1. fast throughput. the ad7643 is a 1.25 msps, charge redistribution, 18-bit sar adc. 2. superior linearity. the ad7643 has no missing 18-bit code. 3. internal reference. the ad7643 has a 2.048 v internal reference with a typical drift of 8 ppm/c and an on-chip temp sensor. 4. single-supply operation. the ad7643 operates from a 2.5 v single supply. 5. serial or parallel interface. versatile parallel (18-, 16-, or 8-bit bus) or 2-wire serial interface arrangement compatible with 2.5 v, 3.3 v, or 5 v logic.
ad7643 rev. 0 | page 2 of 28 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 timing specifications ....................................................................... 5 absolute maximum ratings ............................................................ 7 esd caution .................................................................................. 7 pin configuration and function descriptions ............................. 8 ter mi nolo g y .................................................................................... 11 typical performance characteristics ........................................... 12 applications information .............................................................. 15 circuit information .................................................................... 15 converter operation .................................................................. 15 transfer functions ...................................................................... 16 typical connection diagram ........................................................ 17 analog inputs .............................................................................. 17 multiplexed inputs ..................................................................... 17 driver amplifier choice ........................................................... 18 voltage reference input ............................................................ 18 power supply ............................................................................... 20 conversion control ................................................................... 20 interfaces .......................................................................................... 21 digital interface .......................................................................... 21 parallel interface ......................................................................... 21 serial interface ............................................................................ 22 master serial interface ............................................................... 22 slave serial interface .................................................................. 24 microprocessor interfacing ....................................................... 26 application hints ........................................................................... 27 layout .......................................................................................... 27 evaluating the ad7643 performance ...................................... 27 outline dimensions ....................................................................... 28 ordering guide .......................................................................... 28 revision history 4/06revision 0: initial version
ad7643 rev. 0 | page 3 of 28 specifications avdd = dvdd = 2.5 v; ovdd = 2.3 v to 3.6 v; v ref = 2.5 v; all specifications t min to t max , unless otherwise noted. table 2. parameter conditions min typ max unit resolution 18 bits analog input voltage range v in+ ? v in? ?v ref +v ref v operating input voltage v in+ , v in? to agnd ?0.1 avdd 1 v analog input cmrr f in = 100 khz 58 db input current 1.25 msps throughput 2.5 a input impedance 2 throughput speed complete cycle 800 ns throughput rate 1.25 msps dc accuracy integral linearity error 3 ?3 1.5 +3 lsb 4 no missing codes 18 bits differential linearity error ?1 +1.25 lsb transition noise v ref = 2.5 v 1.7 lsb v ref = 2.048 v 2.0 lsb zero error, t min to t max 5 ?16 +16 lsb zero error temperature drift 1 ppm/c gain error, t min to t max 5 ?22 +22 lsb gain error temperature drift 1 ppm/c power supply sensitivity avdd = 2.5 v 5% 16 lsb ac accuracy dynamic range v ref = 2.5 v 95 db 6 signal-to-noise f in = 1 khz, v ref = 2.5 v 93.5 db f in = 20 khz, v ref = 2.5 v 93.5 db f in = 20 khz, v ref = 2.048 v 92 db f in = 100 khz, v ref = 2.5 v 93 db spurious-free dynamic range f in = 1 khz, v ref = 2.5 v 118 db f in = 20 khz, v ref = 2.5 v 114 db f in = 20 khz, v ref = 2.048 v 111 db f in = 100 khz, v ref = 2.5 v 108 db total harmonic distortion f in = 1 khz, v ref = 2.5 v ?114 db f in = 20 khz, v ref = 2.5 v ?113 db f in = 20 khz, v ref = 2.048 v ?109 db f in = 100 khz, v ref = 2.5 v ?105 db signal-to-(noise + distortion) f in = 1 khz, v ref = 2.5 v 93.5 db f in = 20 khz, v ref = 2.5 v 93.5 db f in = 20 khz, v ref = 2.048 v 91.8 db f in = 100 khz, v ref = 2.5 v 92.5 db ?3 db input bandwidth 50 mhz sampling dynamics aperture delay 1 ns aperture jitter 5 ps rms transient response full-scale step 250 ns internal reference pdref = pdbuf = low output voltage ref @ 25c 2.038 2.048 2.058 v temperature drift ?40c to +85c 8 ppm/c line regulation avdd = 2.5 v 5% 15 ppm/v
ad7643 rev. 0 | page 4 of 28 parameter conditions min typ max unit turn-on settling time c ref = 10 f 5 ms refbufin output voltage refbufin @ 25c 1.19 v refbufin output resistance 6.33 k external reference pdref = pdbuf = high voltage range ref 1.8 2.5 avdd + 0.1 v current drain 1.25 msps throughput 100 a reference buffer pdref = high, pdbuf = low refbufin input voltage range ref = 2.048 v typical 1.05 1.2 1.30 v refbufin input current refbufin = 1.2 v 1 na temperature pin voltage output @ 25c 278 mv temperature sensitivity 1 mv/c output resistance 4.7 k digital inputs logic levels v il ?0.3 +0.6 v v ih 1.7 5.25 v i il ?1 +1 a i ih ?1 +1 a digital outputs data format 7 pipeline delay 8 v ol i sink = 500 a 0.4 v v oh i source = ?500 a ovdd ? 0.3 v power supplies specified performance avdd 2.37 2.5 2.63 v dvdd 2.37 2.5 2.63 v ovdd 2.30 9 3.6 v operating current 10 1.25 msps throughput avdd 11 with internal reference 24 ma dvdd 1.5 ma ovdd 12 0.5 ma power dissipation 10 , 11 with internal reference 1.25 msps throughput 65 80 mw with external reference 1.25 msps throughput 60 75 mw in power-down mode 12 pd = high 2 w temperature range 13 specified performance t min to t max ?40 +85 c 1 when using an external reference. with the internal reference, the input range is ?0.1 v to v ref . 2 see analog inputs section. 3 linearity is tested using endpoints, not best fit. 4 lsb means least significant bit. with the 2.048 v input range, 1 lsb is 15.63 v. 5 see voltage reference input section. thes e specifications do not include the error contribution from the external reference. 6 all specifications in db are referred to a full-scale input fs. tested with an input signal at 0.5 db below full-scale, unless otherwise specified. 7 parallel or serial 18-bit. 8 conversion results are available imme diately after completed conversion. 9 see the absolute maximum ratings section. 10 tested in parallel reading mode. 11 with internal reference, pdref an d pdbuf are low; with external refe rence, pdref and pdbuf are high. 12 with all digital inputs forced to ovdd. 13 consult sales for extended temperature range.
ad7643 rev. 0 | page 5 of 28 timing specifications avdd = dvdd = 2.5 v; ovdd = 2.3 v to 3.6 v; v ref = 2.5 v; all specifications t min to t max , unless otherwise noted. table 3. parameter symbol min typ max unit conversion and reset (refer to figure 30 and figure 31 ) convert pulse width t 1 15 70 1 ns time between conversions t 2 800 ns cnvst low to busy high delay t 3 23 ns busy high all modes (except master serial read after convert) t 4 550 ns aperture delay t 5 1 ns end of conversion to busy low delay t 6 10 ns conversion time t 7 550 ns acquisition time t 8 250 ns reset pulse width t 9 15 ns reset low to busy high delay 2 t 38 10 ns busy high time from reset low 2 t 39 500 ns parallel interface modes (refer to figure 32 to figure 35 ) cnvst low to data valid delay t 10 550 ns data valid to busy low delay t 11 2 ns bus access request to data valid t 12 20 ns bus relinquish time t 13 2 15 ns master serial interface modes 3 (refer to figure 36 and figure 37 ) cs low to sync valid delay t 14 10 ns cs low to internal sclk valid delay 3 t 15 10 ns cs low to sdout delay t 16 10 ns cnvst low to sync delay t 17 135 ns sync asserted to sclk first edge delay t 18 2 ns internal sclk period 4 t 19 8 20 ns internal sclk high 4 t 20 2 ns internal sclk low 4 t 21 2 ns sdout valid setup time 4 t 22 1 ns sdout valid hold time 4 t 23 0 ns sclk last edge to sync delay 4 t 24 0 ns cs high to sync hi-z t 25 10 ns cs high to internal sclk hi-z t 26 10 ns cs high to sdout hi-z t 27 10 ns busy high in master serial read after convert 4 t 28 see table 4 ns cnvst low to sync asserted delay t 29 508 ns sync deasserted to busy low delay t 30 13 ns slave serial interface modes (refer to figure 39 and figure 40 ) external sclk set-up time t 31 5 ns external sclk active edge to sdout delay t 32 1 8 ns sdin set-up time t 33 5 ns sdin hold time t 34 5 ns external sclk period t 35 12.5 ns external sclk high t 36 5 ns external sclk low t 37 5 ns 1 see the conversion control section. 2 see the digital interface se ction and the reset section. 3 in serial interface modes, the sync, sclk, an d sdout timings are defined with a maximum load c l of 10 pf; otherwise, the load is 60 pf maximum. 4 in serial master read during convert mode. see table 4 for serial master read after conver t mode timing specifications.
ad7643 rev. 0 | page 6 of 28 table 4. serial clock timings in master read after convert mode divsclk[1] 0 0 1 1 divsclk[0] symbol 0 1 0 1 unit sync to sclk first edge delay minimum t 18 1 3 3 3 ns internal sclk period minimum t 19 8 16 32 64 ns internal sclk period maximum t 19 20 40 70 135 ns internal sclk high minimum t 20 2 8 16 32 ns internal sclk low minimum t 21 2 8 16 32 ns sdout valid setup time minimum t 22 1 5 5 5 ns sdout valid hold time minimum t 23 0 0.5 10 30 ns sclk last edge to sync delay minimum t 24 0 0.5 9 26 ns busy high width maximum t 28 0.84 1.14 1.72 2.88 s note in serial interface modes, the sync, sclk, and sdout timing are defined with a maximum load c l of 10pf; otherwise, the load is 60pf maximum. 500a i ol 500a i oh 1.4v to output pin c l 50pf 0 6024-002 figure 2. load circuit for digital interface timing, sdut, sc, and scl utputs, c l = 1 pf 0.8v 2v 2v 0.8v 0.8v 2v t delay t delay 0 6024-003 figure 3. voltage reference levels for timing
ad7643 rev. 0 | page 7 of 28 absolute maximum ratings table 5. parameter rating analog inputs/outputs in+ 1 , in?, ref, refbufin, temp, ingnd, refgnd to agnd avdd + 0.3 v to agnd ? 0.3 v ground voltage differences agnd, dgnd, ognd 0.3 v supply voltages avdd, dvdd ?0.3 v to +2.7 v ovdd ?0.3 v to +3.8 v avdd to dvdd 2.8 v avdd, dvdd to ovdd ?3.8 v to +2.8 v digital inputs ?0.3 v to +5.5 v pdref, pdbuf 2 20 ma internal power dissipation 3 700 mw internal power dissipation 4 2.5 w junction temperature 125c storage temperature range C65c to +125c 1 see analog inputs section. 2 see voltage reference input section. 3 specification is for the device in free air: 48-lead lqfp; ja = 91c/w, jc = 30c/w. 4 specification is for the device in free air: 48-lead lfcsp; ja = 26c/w. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
ad7643 rev. 0 | page 8 of 28 pin configuration and fu nction descriptions 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 39 38 37 43 42 41 40 pin 1 identifier top view (not to scale) agnd cnvst pd reset cs rd dgnd agnd avdd mode0 mode1 d0/ob/2c nc = no connect d1/a0 d2/a1 d3 d4/divsclk[0] busy d17 d16 d15 ad7643 d5/divsclk[1] d14 d6/ext/int d7/invsync d8/invsclk d9/rdc/sdin ognd ovdd dvdd dgnd d10/sdout d11/sclk d12/sync d13/rderror pdbuf pdref refbufin temp avdd in+ agnd agnd nc in? refgnd ref 06024-004 dgnd dgnd figure 4. pin configuration table 6. pin function descriptions pin no. mnemonic type 1 description 1, 36, 41, 42 agnd p analog power ground pin. 2, 44 avdd p input analog power pins. nominally 2.5 v. 3, 4 mode[0:1] di data output interface mode selection. interface mode# mode1 mode0 description 0 0 0 18-bit interface 1 0 1 16-bit interface 2 1 0 8-bit (byte) interface 3 1 1 serial interface 5 d0/ob/ 2c di/o when mode[1:0] = 0 (18-bit interface mode), this pi n is bit 0 of the parallel port data output bus and the data coding is straight binary. in all other modes, this pin allows the choice of straight binary/twos complement. when ob/ 2c is high, the digital output is straight binary; when low, the msb is inverted resulting in a twos complement output from its internal shift register. 6, 7 dgnd p connect to digital ground. 8 d1/a0 di/o when mode[1:0] = 0, this pin is bit 1 of the paralle l port data output bus. in all other modes, this input pin controls the form in which data is output as shown in table 7 . 9 d2/a1 di/o when mode[1:0] = 0, this pin is bit 2 of the parallel port data output bus. when mode[1:0] = 1 or 2, this input pin controls the form in which data is output as shown in table 7 . 10 d3 do when mode[1:0] = 0, 1, or 2, this output is used as bit 3 of the parallel port data output bus. this pin is always an output, re gardless of the interface mode. 11, 12 d[4:5] di/o when mode[1:0] = 0, 1, or 2, these pi ns are bit 4 and bit 5 of the parallel port data output bus. or divsclk[0:1] when mode[1:0] = 3 (serial mode), serial clock divi sion selection. when using serial master read after convert mode (ext/ int = low, rdc/sdin = low), these inputs can be used to slow down the internally generated serial clock that clocks the da ta output. in other serial modes, these pins are high impedance outputs. 13 d6 di/o when mode[1:0] = 0, 1, or 2, this output is used as bit 6 of the para llel port data output bus. or ext/ int when mode[1:0] = 3 (serial mode), serial clock source select. this input is used to select the internally generated (master) or external (slave) serial data clock. when ext/ int = low, master mode. the internal serial clock is selected on sclk output. when ext/ int = high, slave mode. the output data is sync hronized to an external clock signal, gated by cs , connected to the sclk input.
ad7643 rev. 0 | page 9 of 28 pin no. mnemonic type 1 description 14 d7 di/o when mode[1:0] = 0, 1, or 2, this output is used as bit 7 of the para llel port data output bus. or invsync when mode[1:0] = 3 (serial mode), invert sy nc select. in serial master mode (ext/ int = low), this input is used to select the active state of the sync signal. when invsync = low, sync is active high. when invsync = high, sync is active low. 15 d8 di/o when mode[1:0] = 0, 1, or 2, this output is used as bit 8 of the para llel port data output bus. or invsclk when mode[1:0] = 3 (serial mode), invert sclk select . in all serial modes, th is input is used to invert the sclk signal. 16 d9 di/o when mode[1:0] = 0, 1, or 2, this output is used as bit 9 of the parall el port data output bus. or rdc when mode[1:0] = 3 (serial mode), read during convert. when using serial master mode (ext/ int = low), rdc is used to select the read mode. when rdc = high, the previous conversion result is output on sdout during conversion and the period of sclk changes (see the master serial interface section). when rdc = low (read after convert), the current result can be output on sdout only when the conversion is complete. or sdin when mode[1:0] = 3 (serial mode), serial da ta in. when using serial slave mode (ext/ int = high), sdin could be used as a data input to daisy-chai n the conversion results from two or more adcs onto a single sdout line. the digital data level on sdin is output on sdout with a delay of 18 sclk periods after the initiation of the read sequence. 17 ognd p input/output interface digital power ground. 18 ovdd p input/output interface digital power. nominally at the same supply as the supply of the host interface (2.5 v or 3 v). 19 dvdd p digital power. nominally at 2.5 v. 20 dgnd p digital power ground. 21 d10 do when mode[1:0] = 0, 1, or 2, this output is used as bit 10 of the parallel port data output bus. or sdout when mode[1:0] = 3 (serial mode), se rial data output. in se rial mode, this pin is used as the serial data output synchronized to sclk. conversion resu lts are stored in an on-chip register. the ad7643 provides the conversion result, msb first, from its internal shift register. the data format is determined by the logic level of ob/ 2c . in master mode, ext/ int = low. sdout is valid on both edges of sclk. in slave mode, ext/ int = high: when invsclk = low, sdout is updated on sclk ri sing edge and valid on the next falling edge. when invsclk = high, sdout is updated on sclk fa lling edge and valid on the next rising edge. 22 d11 di/o when mode[1:0] = 0, 1, or 2, this output is used as bit 11 of the parallel port data output bus. or sclk when mode[1:0] = 3 (serial mode), serial clock. in all serial modes, this pin is used as the serial data clock input or output, dependin g upon the logic state of the ext/ int pin. the active edge where the data sdout is updated depends on the logic state of the invsclk pin. 23 d12 do when mode[1:0] = 0, 1, or 2, this output is used as bit 12 of the parallel port data output bus. or sync when mode[1:0] = 3 (serial mode), frame sync hronization. in serial master mode (ext/ int = low), this output is used as a digital output frame synchronization for use with the internal data clock. when a read sequence is initiated and invsync = low, sync is driven high and remains high while sdout output is valid. when a read sequence is initiated and invsync = high, sync is driven low and remains low while sdout output is valid. 24 d13 do when mode[1:0] = 0, 1, or 2, this output is used as bit 13 of the parallel port data output bus. or rderror when mode[1:0] = 3 (serial mode), read error. in serial slave mode (ext/ int = high), this output is used as an incomplete read error flag. if a data read is started and not completed when the current conversion is complete, the current data is lost and rderror is pulsed high. 25 to 28 d[14:17] do bit 14 to bit 17 of the parallel port data output bus. these pins are always outputs, regardless of the interface mode. 29 busy do busy output. transitions high when a conversion is started and remains high until the conversion is complete and the data is latched into the on-chi p shift register. the falling edge of busy can be used as a data-ready clock signal. 30 dgnd p digital power ground.
ad7643 rev. 0 | page 10 of 28 pin no. mnemonic type 1 description 31 rd di read data. when cs and rd are both low, the interface parallel or serial output bus is enabled. 32 cs di chip select. when cs and rd are both low, the interface parallel or serial output bus is enabled. cs is also used to gate the exte rnal clock in slave serial mode. 33 reset di reset input. when high, resets the ad7643. current conversion, if any, is aborted. falling edge of reset enables the calibration mode indicated by pulsing busy high. refer to the digital interface section. if not used, this pin can be tied to dgnd. 34 pd di power-down input. when high, powers down the adc. power consumption is reduced and conversions are inhibited after the current one is completed. 35 cnvst di conversion start. a falling edge on cnvst puts the internal sample-and-hold into the hold state and initiates a conversion. 37 ref ai/o reference output/input. when pdref/pdbuf = low, the internal reference and buffer are enabled producing 2.048 v on this pin. when pdref/pdbuf = high, the internal reference and buffer are disabled allowing an externally supplied voltage reference up to avdd volts. decoupling is required with or without the internal reference and buffer. refer to the voltage reference input section. 38 refgnd ai reference input analog ground. 39 in? ai differential negative analog input. 40 nc no connect. 43 in+ ai differential positive analog input. 45 temp ao temperature sensor analog output. normally, 278 mv @ 25c with a temperature coefficient of 1 mv/c. this pin can be used to me asure the temperature of the ad7643. see the temperature sensor section. 46 refbufin ai/o internal reference output/reference buffer input. when pdref/pdbuf = low, the internal reference an d buffer are enabled producing the 1.2 v (typical) band gap output on this pin, which needs external decoupling. the internal fixed gain reference buffer uses this to produce 2.048 v on the ref pin. when using an external reference with the internal reference buffer (pdbuf = low, pdref = high), applying 1.2 v on this pin produces 2.048 v on the ref pin. refer to the voltage reference input section. 47 pdref di internal reference power-down input. when low, the internal reference is enabled. when high, the internal reference is powered down and an external reference must been used. 48 pdbuf di internal reference buffer power-down input. when low, the buffer is enabled (must be low when using internal reference). when high, the buffer is powered down. 1 ai = analog input; ai/o = bidirectional analog; ao = analog output; di = digital input; di/o = bidirectional digital; do = dig ital output; p = power. table 7. data bus interface definition mode mode1 mode0 d0/ob/ 2c d1/a0 d2/a1 d[3] d[4:9] d[10:11] d[12:15] d[16:17] description 0 0 0 r[0] r[1] r[2] r[3] r[4:9] r[10:11] r[12:15] r[16:17] 18-bit parallel 1 0 1 ob/ 2c a0 = 0 r[2] r[3] r[4:9] r[10:11] r[12:15] r[16:17] 16-bit high word 1 0 1 ob/ 2c a0 = 1 r[0] r[1] all zeros 16-bit low word 2 1 0 ob/ 2c a0 = 0 a1 = 0 all hi-z r[10:11] r[12:15] r[16:17] 8-bit high byte 2 1 0 ob/ 2c a0 = 0 a1 = 1 all hi-z r[2:3] r[4:7] r[8:9] 8-bit mid byte 2 1 0 ob/ 2c a0 = 1 a1 = 0 all hi-z r[0:1] all zeros 8-bit low byte 2 1 0 ob/ 2c a0 = 1 a1 = 1 all hi-z all zeros r[0:1] 8-bit low byte 3 1 1 ob/ 2c all hi-z serial interface serial interface
ad7643 rev. 0 | page 11 of 28 terminology integral nonlinearity error (inl) linearity error refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. the point used as negative full scale occurs ? lsb before the first code transition. positive full scale is defined as a level 1? lsb beyond the last code transition. the deviation is measured from the middle of each code to the true straight line. differential nonlinearity error (dnl) in an ideal adc, code transitions are 1 lsb apart. differential nonlinearity is the maximum deviation from this ideal value. it is often specified in terms of resolution for which no missing codes are guaranteed. gain error the first transition (from 00000 to 00001) should occur for an analog voltage ? lsb above the nominal negative full scale (?2.0479922 v for the 2.048 v range). the last transition (from 11110 to 11111) should occur for an analog voltage 1? lsb below the nominal full scale (+2.0479766 v for the 2.048 v range). the gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition from the difference between the ideal levels. zero error the zero error is the difference between the ideal midscale input voltage (0 v) and the actual voltage producing the midscale output code. dynamic range it is the ratio of the rms value of the full scale to the rms noise measured with the inputs shorted together. the value for dynamic range is expressed in decibels. signal-to-noise ratio (snr) snr is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, excluding harmonics and dc. the value for snr is expressed in decibels. total harmonic distortion (thd) thd is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in decibels. signal to (noise + distortion) ratio (sinad) sinad is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, including harmonics but excluding dc. the value for sinad is expressed in decibels. spurious-free dynamic range (sfdr) the difference, in decibels (db), between the rms amplitude of the input signal and the peak spurious signal. effective number of bits (enob) enob is a measurement of the resolution with a sine wave input. it is related to sinad and is expressed in bits by enob = [( sinad db ? 1.76)/6.02] aperture delay aperture delay is a measure of the acquisition performance and is measured from the falling edge of the cnvst input to when the input signal is held for a conversion. transient resp onse the time required for the ad7643 to achieve its rated accuracy after a full-scale step function is applied to its input. reference voltage temperature coefficient it is derived from the typical shift of output voltage at 25c on a sample of parts maximum and minimum reference output voltage (v ) measured at t , t(25c), and t . it is expressed in ppm/c using ref min max () () ( ) () () 6 10 c25 cppm/ ? ? = m in m a x ref ref ref ref tt v minvmaxv tcv where: v ref ( max ) = maximum v ref at t min , t(25c), or t max v ref ( min ) = minimum v ref at t min , t(25c), or t max v ref (25 c ) = v ref at 25c t max = +85c t min = C40c
ad7643 rev. 0 | page 12 of 28 typical performance characteristics 3.0 ?3.0 0 262144 code inl (lsb) 2.5 2.0 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 ?2.0 ?2.5 65536 131072 196608 06024-005 figure 5. integral nonlinearity vs. code 40000 0 1ffee 1ffef 1fff0 1fff1 1fff2 1fff3 1fff4 1fff5 1fff6 1fff7 1fff8 1fff9 1fffa 1fffb 1fffc 1fffd 1fffe 1ffff code in hex counts 06024-006 35000 30000 25000 20000 15000 10000 5000 = 1.67 v ref = 2.5v 013 16 30 228 59 33606 26875 23521 17320 4848 3062 13376 6371 1295 488 figure 6. histogram of 131,072 conversions of a dc input at the code center (external reference) 2.0486 2.0484 2.0482 2.0480 2.0478 2.0476 2.0474 2.0472 2.0470 ?55 12510585654525 5 ?15?35 temperature (c) v ref (v) 06024-007 figure 7. typical reference voltage output vs. temperature (2 units) 1.25 ?1.0 0 262144 code dnl (lsb) 0.5 65536 131072 196608 1.0 0 ?0.5 06024-008 figure 8. differential nonlinearity vs. code 35000 0 20027 20028 20029 2002a 2002b 2002c 2002d 2002e 2002f 20030 20031 20032 20033 20034 20035 20036 20037 20038 code in hex counts 06024-009 30000 25000 20000 15000 10000 5000 21 28 305 665 297 108 32 4726 5401 15505 18613 28621 24350 16141 3807 10173 2306 = 2.04 v ref = 2.048v figure 9. histogram of 131,072 conversions of a dc input at the code center (internal reference) 12 ?12 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 ?55 12510585654525 5 ?15?35 temperature (c) zero error, gain error (lsb) 06024-010 gain error zero error figure 10. zero error, gain error vs. temperature
ad7643 rev. 0 | page 13 of 28 frequency (khz) amplitude (db of full scale) 0 ?180 06 0 0 0 ?180 06 0 0 frequency (khz) amplitude (db of full scale) 06024-011 ?20 ?40 ?60 ?80 ?100 ?120 ?140 ?160 100 200 300 400 500 f s = 1.25msps f in = 20.03khz snr = 93.4db thd = ?113db sfdr = 108db sinad = 93.4db 06024-014 ?20 ?40 ?60 ?80 ?100 ?120 ?140 ?160 100 200 300 400 500 f s = 1.25msps f in = 100.03khz snr = 93db thd = ?106db sfdr = 109db sinad = 92.8db figure 11. fft 20 khz 95 75 1 1000 frequency (khz) snr, sinad (db) sinad enob snr 06024-012 93 91 89 87 85 83 81 79 77 16.0 12.0 enob (bits) 15.6 15.2 14.8 14.4 14.0 13.6 13.2 12.8 12.4 10 100 figure 12. snr, sinad, and enob vs. frequency ? 70 ?140 1 1000 frequency (khz) thd, harmonics (db) sfdr thd 06024-013 120 20 sfdr (db) 110 100 90 80 70 60 50 40 30 10 100 ?80 ?90 ?100 ?110 ?120 ?130 third harmonic second harmonic figure 13. thd, harmonics, and sfdr vs. frequency figure 14. fft 100 khz 95 94 93 92 91 90 19 18 17 16 15 14 ?55 125105 snr 856545 25 5 ?15 ?35 temperature (c) snr, sinad (db) enob (bits) 06024-015 enob sinad figure 15. snr, sinad, and enob vs. temperature ? 85 ?90 ?95 ?100 ?105 ?110 ?115 ?120 ?125 ?130 ?135 ?140 ?145 120 60 70 80 90 100 110 ?55 12510585654525 5 ?15?35 temperature (c) thd, harmonics (db) sfdr (db) 06024-016 sfdr thd second harmonic third harmonic figure 16. thd, harmonics, and sfdr vs. temperature
ad7643 rev. 0 | page 14 of 28 96.0 93.0 ?60 0 input level (db) snr, sinad referred to full scale (db) sinad snr 06024-017 95.5 95.0 94.5 94.0 93.5 ?50 ?40 ?30 ?20 ?10 figure 17. snr and sinad vs. input level (referred to full scale) 16 0 125 ?55 temperature (c) operating currents ( a ) 14 12 10 8 6 4 2 ?35?155 25456585105 dvdd ovdd, 3.3v ovdd, 2.5v avdd 06024-018 figure 18. power-down operating currents vs. temperature 100k 0.01 10 10m sampling rate (sps) operating currents (a) 100 1k 10k 100k 1m 0.1 1 10 100 1k 10k avdd dvdd ovdd = 3.3v ovdd = 2.5v pdref = pdbuf = high 06024-019 figure 19. operating current vs. sampling rate 20 4 0 c l (pf) t 12 delay (ns) 18 16 14 12 10 8 6 50 100 150 200 ovdd = 2.5v @ 85c ovdd = 3.3v @ 85c ovdd = 3.3v @ 25c ovdd = 2.5v @ 25c 06024-020 figure 20. typical delay vs. load capacitance c l
ad7643 rev. 0 | page 15 of 28 applications information sw+ comp sw? in+ ref refgnd lsb msb 131,072c 65,536c 4c 2c c c control logic switches control busy output code cnvst in? 4c 2c c c lsb msb agnd agnd 131,072c 65,536c 06024-021 figure 21. adc simplified schematic circuit information the ad7643 is a very fast, low power, single-supply, precise 18-bit adc using successive approximation architecture. the ad7643 is capable of converting 1,250,000 samples per second (1.25 msps). the ad7643 provides the user with an on-chip, track-and-hold, successive approximation adc that does not exhibit any pipeline or latency, making it ideal for multiple multiplexed channel applications. the ad7643 can operate from a single 2.5 v supply and interface to either 5 v, 3.3 v, or 2.5 v digital logic. it is housed in a pb-free, 48-lead lqfp package or a tiny 48-lead lfcsp package, which combines space savings with flexibility and allows the ad7643 to be configured as either a serial or a parallel interface. the ad7643 is pin-to-pin compatible with the ad7641 and is a speed upgrade of the ad7674 , ad7678 , and ad7679 . converter operation the ad7643 is a successive approximation adc based on a charge redistribution dac. figure 21 shows the simplified schematic of the adc. the capacitive dac consists of two identical arrays of 16 binary weighted capacitors that are connected to the two comparator inputs. during the acquisition phase, terminals of the array tied to the comparators input are connected to agnd via sw+ and sw?. all independent switches are connected to the analog inputs. therefore, the capacitor arrays are used as sampling capacitors and acquire the analog signal on the in+ and in? inputs. a conversion phase is initiated once the acquisition phase is complete and the cnvst input goes low. when the conversion phase begins, sw+ and sw? are opened first. the two capacitor arrays are then disconnected from the inputs and connected to the refgnd input. therefore, the differential voltage between the inputs (in+ and in?) captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. by switching each element of the capacitor array between refgnd and ref, the comparator input varies by binary weighted voltage steps (v ref /2, v ref /4 throughv ref /262144). the control logic toggles these switches, starting with the msb first, to bring the comparator back into a balanced condition. after the completion of this process, the control logic generates the adc output code and brings busy output low.
ad7643 rev. 0 | page 16 of 28 transfer functions using the ob/ 2c digital input, except in 18-bit interface mode, the ad7643 offers two output codings: straight binary and twos complement. the lsb size with v ref = 2.048 v is 2 v ref / 262,144, which is 15.623 v. refer to figure 22 and table 8 for the ideal transfer characteristic. 000...000 000...001 000...010 111...101 111...110 111...111 adc code (straight binary) analog input +fsr ? 1.5 lsb +fsr ? 1 lsb ?fsr + 1 lsb ?fsr ?fsr + 0.5 lsb 06024-022 figure 22. adc ideal transfer function table 8. output codes and ideal input voltages digital output code (hex) description analog input v ref = 2.048 v straight binary twos complement fsr ?1 lsb +2.0479844 v 0x3ffff 1 0x1ffff 1 fsr ? 2 lsb +2.0479688 v 0x3fffe 0x1fffe midscale + 1 lsb +15.625 v 0x20001 0x00001 midscale 0 v 0x20000 0x00000 midscale ? 1 lsb ?15.625 v 0x1ffff 0x3ffff ?fsr + 1 lsb ?2.0479844 v 0x00001 0x20001 ?fsr ?2.048 v 0x00000 2 0x20000 2 1 this is also the code fo r overrange analog input (v in+ ? v in? above +v ref ? v refgnd ). 2 this is also the code fo r underrange analog input (v in+ ? v in? below ?v ref + v refgnd ). rd cs 100nf 100nf avdd 10f 100nf agnd dgnd dvdd ovdd ognd cnvst busy sdout sclk reset pd refbufin 10 ? d clock ad7643 microconverter/ microprocessor/ dsp serial port digital interface supply (2.5v or 3.3v) analog supply (2.5v) ovdd digit a l supply (2.5v) in+ in? u2 15 ? note 5 50 ? 50pf note 1 analog input + c c c c 2.7nf 2.7nf u1 15 ? note 1 mode0 mode1 d0/ob/2c refgnd ref pdbuf pdref 100nf analog input ? note 2 note 2 note 3 note 4 note 3 note 7 note 6 10f 10f c ref 10f 10k ? 50pf 1. see analog inputs section. 2 . the ad8021 is recommended. see driver amplifier choice section. 3 . the configuration shown is using the internal reference. see voltage reference input section. 4 . a 10f ceramic capacitor (x5r, 1206 size) is recommended (for example, panasonic ecj3yb0j106m). see voltage reference input section. 5. option, see power supply section. 6. option, see power-up section. 7. optional low jitter cnvst, see conversion control section. 06024-023 figure 23. typical connection diagram
ad7643 rev. 0 | page 17 of 28 typical connection diagram figure 23 shows a typical connection diagram for the ad7643. different circuitry shown in this diagram is optional and is discussed in the following sections. analog inputs figure 24 shows an equivalent circuit of the input structure of the ad7643. the two diodes, d 1 and d 2 , provide esd protection for the analog inputs in+ and in?. care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 0.3 v, because this causes the diodes to become forward- biased and to start conducting current. these diodes can handle a forward-biased current of 100 ma maximum. for instance, these conditions could eventually occur when the input buffers u1 or u2 supplies are different from avdd. in such a case, an input buffer with a short-circuit current limitation can be used to protect the part. d 1 r in c in d 2 in+ or in? agnd a v dd c pin 06024-024 figure 24. ad7643 simplified analog input the analog input of the ad7643 is a true differential structure. by using this differential input, small signals common to both inputs are rejected, as shown in figure 25 , representing the typical cmrr over frequency with internal and external references. 65 45 1 10000 frequency (khz) cmrr (db) 10 100 1000 60 55 50 int ref ext ref 06024-025 figure 25. analog input cmrr vs. frequency during the acquisition phase for ac signals, the impedance of the analog inputs, in+ and in?, can be modeled as a parallel combination of capacitor c pin and the network formed by the series connection of r in and c in . c pin is primarily the pin capacitance. r in is typically 175 and is a lumped component comprised of some serial resistors and the on resistance of the switches. c in is typically 12 pf and is mainly the adc sampling capacitor. during the conversion phase, when the switches are opened, the input impedance is limited to c pin . r in and c in make a 1-pole, low-pass filter that has a typical ?3 db cutoff frequency of 50 mhz, thereby reducing an undesirable aliasing effect and limiting the noise coming from the inputs. because the input impedance of the ad7643 is very high, the ad7643 can be driven directly by a low impedance source without gain error. to further improve the noise filtering achieved by the ad7643s analog input circuit, an external 1-pole rc filter between the amplifiers outputs and the adc analog inputs can be used, as shown in figure 23 . however, large source impedances significantly affect the ac performance, especially the total harmonic distortion (thd). the maximum source impedance depends on the amount of thd that can be tolerated. the thd degrades as a function of the source impedance and the maximum input frequency, as shown in figure 26 . ? 70 ?110 1 10 100 1000 input frequency (khz) thd (db) r s = 500 ? r s = 100 ? r s = 10 ? r s = 50 ? 06024-026 ?75 ?80 ?85 ?90 ?95 ?100 ?105 figure 26. thd vs. analog input frequency and source resistance multiplexed inputs when using the full 1.25 msps throughput in multiplexed applications for a full-scale step, the rc filter, as shown in figure 23 , does not settle in the required acquisition time, t 8 . these values are chosen to optimize the best snr performance of the ad7643. to use the full 1.25 msps throughput in multiplexed applications, the rc should be adjusted to satisfy t 8 (which is ~ 8.5 rc time constant). however, lowering r and c increases the rc filter bandwidth and allows more noise into the ad7643, which degrades snr. to preserve the snr performance in these applications using the rc filter shown in figure 23 , the ad7643 should be run with t 8 > 350 ns; or approximately 1/(t 7 + t 8 ) ~ 1.12 msps.
ad7643 rev. 0 | page 18 of 28 driver amplifier choice although the ad7643 is easy to drive, the driver amplifier needs to meet the following requirements: ? for multichannel, multiplexed applications, the driver amplifier and the ad7643 analog input circuit must be able to settle for a full-scale step of the capacitor array at an 18-bit level (0.0004%). in the amplifiers data sheet, settling at 0.1% to 0.01% is more commonly specified. this could differ significantly from the settling time at an 18-bit level and should be verified prior to driver selection. the ad8021 op amp, which combines ultralow noise and high gain bandwidth, meets this settling time requirement even when used with gains up to 13. ? the noise generated by the driver amplifier needs to be kept as low as possible to preserve the snr and transition noise performance of the ad7643. the noise coming from the driver is filtered by the ad7643 analog input circuit 1-pole, low-pass filter made by r in and c in or by the external filter, if one is used. the snr degradation due to the amplifier is () () ? ? ? ? ? ? ? ? ? ? ? ? ? ? + + = ? ? + ? 2 2 2 2 900 30 20log n 3db n 3db loss ne f ne f snr where: f C3db is the input bandwidth of the ad7643 (50 mhz) or the cutoff frequency of the input rc filter shown in figure 23 (3.9 mhz), if one is used. n is the noise factor of the amplifier (1 in buffer configuration). e n+ and e n? are the equivalent input voltage noise densities of the op amps connected to in+ and in?, in nv/hz. this approximation can be used when the resistances used around the amplifier are small. if larger resistances are used, their noise contributions should also be root-sum squared. for instance, when using op amps with an equivalent input noise density of 2.1 nv/hz, such as the ad8021 , with a noise gain of 1 when configured as a buffer, degrades the snr by only 0.25 db when using the rc filter in figure 23 , and by 2.5 db without it. ? the driver needs to have a thd performance suitable to that of the ad7643. figure 13 gives the thd vs. frequency that the driver should exceed. the ad8021 meets these requirements and is appropriate for almost all applications. the ad8021 needs a 10 pf external compensation capacitor that should have good linearity as an npo ceramic or mica type. moreover, the use of a noninverting 1 gain arrangement is recommended and helps to obtain the best signal-to-noise ratio. the ad8022 can also be used when a dual version is needed and a gain of 1 is present. the ad829 is an alternative in applications where high frequency (above 100 khz) performance is not required. in applications with a gain of 1, an 82 pf compensation capacitor is required. the ad8610 is an option when low bias current is needed in low frequency applications. single-to-differential driver for applications using unipolar analog signals, a single-ended- to-differential driver, as shown in figure 27 , allows for a differential input into the part. this configuration, when provided an input signal of 0 to v ref , produces a differential v ref with midscale at v ref /2. the 1-pole filter using r = 15 and c = 2.7 nf provides a corner frequency of 3.9 mhz. if the application can tolerate more noise, the ad8139 differential driver can be used. ad8021 analog input ( unipolar 0 v to 2.048v) ad8021 in+ in? ad7643 ref 10f 15 ? 15 ? 100nf 2.7nf 2.7nf u2 u1 10pf 10pf 5k? 5k ? 590? 590? 06024-027 figure 27. single-ended-to- differential driver circuit (internal reference buffer used) voltage reference input the ad7643 allows the choice of either a very low temperature drift internal voltage reference, an external 1.2 v reference that can be buffered using the internal reference buffer, or an external reference. unlike many adcs with internal references, the internal reference of the ad7643 provides excellent performance and can be used in almost all applications.
ad7643 rev. 0 | page 19 of 28 internal reference (pdbuf = low, pdref = low) to use the internal reference, the pdref and pdbuf inputs must both be low. this produces a 1.2 v band gap output on refbufin, which is amplified by the internal buffer and results in a 2.048 v reference on the ref pin. the internal reference is temperature compensated to 2.048 v 10 mv. the reference is trimmed to provide a typical drift of 8 ppm/c. this typical drift characteristic is shown in figure 7 . the output resistance of refbufin is 6.33 k (minimum) when the internal reference is enabled. it is necessary to decouple this with a ceramic capacitor greater than 100 nf. therefore, the capacitor provides an rc filter for noise reduction. because the output impedance of refbufin is typically 6.33 k, relative humidity (among other industrial contaminates) can directly affect the drift characteristics of the reference. typically, a guard ring is used to reduce the effects of drift under such circumstances. however, because the ad7643 has a fine lead pitch, guarding this node is not practical. therefore, in these industrial and other types of applications, it is recommended to use a conformal coating, such as dow corning? 1-2577 or humiseal? 1b73. external 1.2 v reference and internal buffer (pdbuf = low, pdref = high) to use an external reference along with the internal buffer, pdref should be high and pdbuf should be low. this powers down the internal reference and allows an external 1.2 v reference to be applied to refbufin, producing 2.048 v (typically) on the ref pin. external 2.5 v reference (pdbuf = high, pdref = high) to use an external 2.5 v reference directly on the ref pin, pdref and pdbuf should both be high. for improved drift performance, an external reference, such as the ad780 or adr431 , can be used. the advantages of directly using the external voltage reference are: ? the snr and dynamic range improvement (about 1.7 db) resulting from the use of a reference voltage very close to the supply (2.5 v) instead of a typical 2.048 v reference when the internal reference is used. this is calculated by ? ? ? ? ? ? = 50.2 048.2 log20 snr ? the power savings when the internal reference is powered down (pdref high). pdref and pdbuf power down the internal reference and the internal reference buffer, respectively. the input current of pdref and pdbuf should never exceed 20 ma. this can occur when the driving voltage is above avdd (for instance, at power-up). in this case, a 125 series resistor is recommended. reference decoupling whether using an internal or external reference, the ad7643 voltage reference input (ref) has a dynamic input impedance; therefore, it should be driven by a low impedance source with efficient decoupling between the ref and refgnd inputs. this decoupling depends on the choice of the voltage reference but usually consists of a low esr capacitor connected to ref and refgnd with minimum parasitic inductance. a 10 f (x5r, 1206 size) ceramic chip capacitor (or 47 f tantalum capacitor) is appropriate when using either the internal reference or one of the recommended reference voltages. the placement of the reference decoupling is also important to the performance of the ad7643. the decoupling capacitor should be mounted on the same side as the adc right at the ref pin with a thick pcb trace. the refgnd should also connect to the reference decoupling capacitor with the shortest distance. for applications that use multiple ad7643 devices, it is more effective to use an external reference with the internal reference buffer to buffer the reference voltage. however, because the reference buffers are not unity gain, ratiometric, simultaneously sampled designs should use an external reference and external buffer, such as the ad8031 / ad8032 ; therefore, preserving the same reference level for all converters. the voltage reference temperature coefficient (tc) directly impacts full scale; therefore, in applications where full-scale accuracy matters, care must be taken with the tc. for instance, a 4 ppm/c tc of the reference changes full scale by 1 lsb/c. note that v ref can be increased to avdd + 0.1 v. because the input range is defined in terms of v ref , this would essentially increase the range to 0 v to 2.8 v with an avdd = 2.7 v. temperature sensor the temp pin measures the temperature of the ad7643. to improve the calibration accuracy over the temperature range, the output of the temp pin is applied to one of the inputs of the analog switch (such as, adg779 ), and the adc itself is used to measure its own temperature. this configuration is shown in figure 28 . adg779 ad8021 c c analog input (unipolar) ad7643 in+ temperature sensor temp 06024-028 figure 28. use of the temperature sensor
ad7643 rev. 0 | page 20 of 28 power supply the ad7643 uses three sets of power supply pins: an analog 2.5 v supply avdd, a digital 2.5 v core supply dvdd, and a digital input/output interface supply ovdd. the ovdd supply allows direct interface with any logic working between 2.3 v and 5.25 v. to reduce the number of supplies needed, the digital core (dvdd) can be supplied through a simple rc filter from the analog supply, as shown in figure 23 . power sequencing the ad7643 is independent of power supply sequencing and thus free from supply induced voltage latch-up. in addition, it is insensitive to power supply variations over a wide frequency range, as shown in figure 29 . 65.0 45.0 1 10000 frequency (khz) psrr (db) 10 100 1000 62.5 60.0 57.5 55.0 52.5 50.0 47.5 int ref ext ref 06024-029 figure 29. psrr vs. frequency power-up at power-up, or when returning to operational mode from the power-down mode (pd = high), the ad7643 engages an initialization process. during this time, the first 128 conversions should be ignored or the reset input could be pulsed to engage a faster initialization process. refer to the digital interface section for reset and timing details. a simple power-on reset circuit, as shown in figure 23 , can be used to minimize the digital interface. as ovdd powers up, the capacitor is shorted and brings reset high; it is then charged returning reset to low. however, this circuit only works when powering up the ad7643 because the power-down mode (pd = high) does not power down any of the supplies and as a result, reset is low. it should be noted that the digital interface remains active even during the acquisition phase. to reduce the operating digital supply currents even further, drive the digital inputs close to the power rails (that is, ovdd and ognd). conversion control the ad7643 is controlled by the cnvst input. a falling edge on cnvst is all that is necessary to initiate a conversion. detailed timing diagrams of the conversion process are shown in figure 30 . once initiated, it cannot be restarted or aborted, even by the power-down input, pd, until the conversion is complete. the cnvst signal operates independently of cs and rd signals. busy mode convert acquire acquire convert cnvst t 1 t 2 t 4 t 3 t 5 t 6 t 7 t 8 06024-030 figure 30. basic conversion timing for optimal performance, the rising edge of cnvst should not occur after the maximum cnvst low time, t 1 , or until the end of conversion. although cnvst is a digital signal, it should be designed with special care with fast, clean edges and levels with minimum overshoot and undershoot or ringing. the cnvst trace should be shielded with ground and a low value serial resistor (for example, 50 ) termination should be added close to the output of the component that drives this line. in addition, a 50 pf capacitor is recommended to further reduce the effects of overshoot and undershoot as shown in figure 23 . for applications where snr is critical, the cnvst signal should have very low jitter. this can be achieved by using a dedicated oscillator for cnvst generation, or by clocking cnvst with a high frequency, low jitter clock, as shown in figure 23 .
ad7643 rev. 0 | page 21 of 28 interfaces digital interface the ad7643 has a versatile digital interface that can be set up as either a serial or a parallel interface with the host system. the serial interface is multiplexed on the parallel data bus. the ad7643 digital interface also accommodates 2.5 v, 3.3 v, or 5 v logic with either ovdd at 2.5 v or 3.3 v. ovdd defines the logic high output voltage. in most applications, the ovdd supply pin of the ad7643 is connected to the host system interface 2.5 v or 3.3 v digital supply. by using the d0/ob/ 2c input pin, either twos complement or straight binary coding can be used. the two signals cs and rd control the interface. when at least one of these signals is high, the interface outputs are in high impedance. usually, cs allows the selection of each ad7643 in multicircuit applications and is held low in a single ad7643 design. rd is generally used to enable the conversion result on the data bus. reset the reset input is used to reset the ad7643 and generate a fast initialization. a rising edge on reset aborts the current conversion (if any) and tristates the data bus. the falling edge of reset clears the data bus and engages the initialization process indicated by pulsing busy high. conversions can take place after the falling edge of busy. refer to figure 31 for the reset timing details. reset data busy cnvst t 38 t 39 t 8 t 9 06024-031 figure 31. reset timing parallel interface the ad7643 is configured to use the parallel interface for an 18-bit, 16-bit, or 8-bit bus width according to table 7 . master parallel interface data can be continuously read by tying cs and rd low, thus requiring minimal microprocessor connections. however, in this mode, the data bus is always driven and cannot be used in shared bus applications, unless the device is held in reset. figure 32 details the timing for this mode. t 1 busy data bus previous conversion data new data cnvst cs = rd = 0 t 10 t 4 t 11 t 3 06024-032 figure 32. master parallel data timing for reading (continuous read) slave parallel interface in slave parallel reading mode, the data can be read either after each conversion, which is during the next acquisition phase, or during the following conversion, as shown in figure 33 and figure 34 , respectively. when the data is read during the conversion, it is recommended that it is read-only during the first half of the conversion phase. this avoids any potential feedthrough between voltage transients on the digital interface and the most critical analog conversion circuitry. current conversion t 13 t 12 busy data bus rd cs 06024-033 figure 33. slave parallel data timing for reading (read after convert) previous conversion t 13 t 12 t 3 busy data bus cnvst, rd cs = 0 t 4 t 1 06024-034 figure 34. slave parallel data timing for reading (read during convert)
ad7643 rev. 0 | page 22 of 28 16-bit and 8-bit interface (master or slave) in the 16-bit (mode[1:0] = 1) and 8-bit (mode[1:0] = 2) interfaces, the a0/a1 pins allow a glueless interface to a 16- or 8-bit bus, as shown in figure 35 . by connecting a0/a1 to an address line(s), the data can be read in two words for a 16-bit interface, or three bytes for an 8-bit interface. this interface can be used in both master and slave parallel reading modes. refer to table 7 for the full details of the interface. cs, rd a1 d[17:2] hi-z high word low word hi-z t 12 t 13 high byte a0 mid byte low byte d[17:10] t 12 hi-z hi-z t 12 06024-035 figure 35. 8-bit and 16-bit parallel interface serial interface the ad7643 is configured to use the serial interface when mode[1:0] = 3. the ad7643 outputs 18 bits of data, msb first, on the sdout pin. this data is synchronized with the 18 clock pulses provided on the sclk pin. the output data is valid on both the rising and falling edge of the data clock. master serial interface internal clock the ad7643 is configured to generate and provide the serial data clock sclk when the ext/ int pin is held low. the ad7643 also generates a sync signal to indicate to the host when the serial data is valid. the serial clock sclk and the sync signal can be inverted. depending on the read during convert input, rdc/sdin, the data can be read after each conversion or during the following conversion. figure 36 and figure 37 show detailed timing diagrams of these two modes. usually, because the ad7643 is used with a fast throughput, the master read during conversion mode is the most recommended serial mode. in this mode, the serial clock and data toggle at appropriate instants, minimizing potential feedthrough between digital activity and critical conversion decisions. in this mode, the sclk period changes because the lsbs require more time to settle and the sclk is derived from the sar conversion cycle. in read after conversion mode, it should be noted that unlike other modes, the busy signal returns low after the 18 data bits are pulsed out and not at the end of the conversion phase, resulting in a longer busy width. as a result, the maximum throughput cannot be achieved in this mode. in addition, in read after convert mode, the sclk frequency can be slowed down to accommodate different hosts using the divsclk[1:0] inputs. refer to table 4 for the sclk timing details when using these inputs.
ad7643 rev. 0 | page 23 of 28 busy sync sclk s dout 123 161718 d17 d16 d2 d1 d0 x rdc/sdin = 0 invsclk = invsync = 0 cnvst cs, rd ext/int = 0 t 23 t 22 t 16 t 15 t 14 t 29 t 19 t 21 t 20 t 18 t 28 t 30 t 24 t 25 t 26 t 27 t 3 divsclk[1:0] = 0 06024-036 figure 36. master serial data timing for reading (read after convert) ext/int = 0 rdc/sdin = 1 invsclk = invsync = 0 d17 d16 d2 d1 d0 x 123 161718 busy sync sclk sdout cnvst cs, rd t 23 t 18 t 15 t 14 t 17 t 3 t 22 t 16 t 1 t 25 t 26 t 24 t 27 t 19 t 20 t 21 0 6024-037 figure 37. master serial data timing for reading (read previous conversion during convert)
ad7643 rev. 0 | page 24 of 28 slave serial interface external clock the ad7643 is configured to accept an externally supplied serial data clock on the sclk pin when the ext/ int pin is held high. in this mode, several methods can be used to read the data. the external serial clock is gated by cs . when cs and rd are both low, the data can be read after each conversion or during the following conversion. the external clock can be either a continuous or a discontinuous clock. a discontinuous clock can be either normally high or normally low when inactive. figure 39 and figure 40 show the detailed timing diagrams of these methods. while the ad7643 is performing a bit decision, it is important that voltage transients be avoided on digital input/output pins or degradation of the conversion result could occur. this is particularly important during the second half of the conversion phase because the ad7643 provides error correction circuitry that can correct for an improper bit decision made during the first half of the conversion phase. for this reason, it is recommended that when an external clock is being provided, a discontinuous clock is toggled only when busy is low or, more importantly, that it does not transition during the latter half of busy high. external discontinuous clock data read after conversion figure 39 shows the detailed timing diagrams of this method. after a conversion is complete, indicated by busy returning low, the conversion result can be read while both cs and rd are low. data is shifted out msb first with 18 clock pulses and is valid on the rising and falling edges of the clock. among the advantages of this method is the fact that conversion performance is not degraded because there are no voltage transients on the digital interface during the conversion process. another advantage is the ability to read the data at any speed up to 80 mhz, which accommodates both the slow digital host interface and the fast serial reading. it is also possible to begin to read data after conversion and continue to read the last bits after a new conversion is initiated. in this reading mode, it is recommended to pause digital activity just prior to initiating a conversion (sclk should be held high or low). once the conversion has begun, the reading can continue. also, in this mode, the use of a slower clock speed can be used to read the data because the total reading time is the acquisition time, t 8 + half of the conversion time, t 7 (t 8 + ? t 7 , see the external clock data read during previous conversion section). finally, in this mode only, the ad7643 provides a daisy-chain feature using the rdc/sdin pin for cascading multiple converters together. this feature is useful for reducing component count and wiring connections when desired, as, for instance, in isolated multiconverter applications. an example of the concatenation of two devices is shown in figure 38 . simultaneous sampling is possible by using a common cnvst signal. it should be noted that the rdc/sdin input is latched on the edge of sclk opposite to the one used to shift out the data on sdout. therefore, the msb of the upstream converter just follows the lsb of the downstream converter on the next sclk cycle. sclk sdout rdc/sdin ad7643 #1 (downstream) ad7643 #2 (upstream) busy out busy busy data out sclk rdc/sdin sdout sclk in cnvst in cnvst cs cnvst cs cs in 06024-038 figure 38. two ad7643 devices in a daisy-chain configuration external clock data read during previous conversion figure 40 shows the detailed timing diagrams of this method. during a conversion, while cs and rd are both low, the result of the previous conversion can be read. the data is shifted out, msb first, with 18 clock pulses and is valid on both the rising and falling edge of the clock. the 18 bits have to be read before the current conversion is complete; otherwise, rderror is pulsed high and can be used to interrupt the host interface to prevent incomplete data reading. there is no daisy-chain feature in this mode, and the rdc/sdin input should always be tied either high or low. to reduce performance degradation due to digital activity, a fast discontinuous clock of at least 67 mhz is recommended to ensure that all the bits are read during the first half of the sar conversion phase, t 7 , because the adc can correct for errors introduced by digital activity during this time.
ad7643 rev. 0 | page 25 of 28 sclk s dout d17 d16 d1 d0 d15 x17 x16 x15 x1 x0 y17 y16 busy sdin invsclk = 0 x17 x16 x 123 1617181920 ext/int = 1 cs rd = 0 t 33 t 16 t 34 t 31 t 32 t 35 t 36 t 37 06024-039 figure 39. slave serial data timing for reading (read after convert) s dout sclk d1 d0 x d17 d16 d15 1 2 3 17 18 busy ext/int = 1 invsclk = 0 cnvst cs rd = 0 t 16 t 31 t 32 t 35 t 3 t 36 t 37 4 d2 16 0 6024-040 figure 40. slave serial data timing for reading (read previous conversion during convert)
ad7643 rev. 0 | page 26 of 28 microprocessor interfacing the ad7643 is ideally suited for traditional dc measurement applications supporting a microprocessor, and ac signal processing applications interfacing to a digital signal processor. the ad7643 is designed to interface with a parallel 8-bit or 16-bit wide interface or with a general-purpose serial port or i/o ports on a microcontroller. a variety of external buffers can be used with the ad7643 to prevent digital noise from coupling into the adc. the spi interface (adsp-219x) section illustrates the use of the ad7643 with the adsp-219x spi-equipped dsp. spi interface (adsp-219x) figure 41 shows an interface diagram between the ad7643 and an spi-equipped dsp, the adsp-219x. to accommodate the slower speed of the dsp, the ad7643 acts as a slave device and data must be read after conversion. this mode also allows the daisy-chain feature. the convert command can be initiated in response to an internal timer interrupt. the 18-bit output data are read with three spi byte access. the reading process can be initiated in response to the end-of-conversion signal (busy going low) using an interrupt line of the dsp. the serial peripheral interface (spi) on the adsp-219x is configured for master mode (mstr) = 1, clock polarity bit (cpol) = 0, clock phase bit (cpha) = 1, and the spi interrupt enable (timod) = 00 by writing to the spi control register (spicltx). it should be noted that to meet all timing requirements, the spi clock should be limited to 17 mbps, allowing it to read an adc result in less than 1 s. when a higher sampling rate is desired, it is recommended to use one of the parallel interface modes. busy cs sdout sclk cnvst ad7643 pfx spixsel (pfx) misox sckx pfx or tfsx adsp-219x 1 dvdd mode0 mode1 ext/int rd invsclk 1 additional pins omitted for clarity. 06024-041 figure 41. interfacing the ad7643 to adsp-219x
ad7643 rev. 0 | page 27 of 28 application hints layout while the ad7643 has very good immunity to noise on the power supplies, exercise care with the grounding layout. to facilitate the use of ground planes that can be easily separated, design the printed circuit board that houses the ad7643 so that the analog and digital sections are separated and confined to certain areas of the board. digital and analog ground planes should be joined in only one place, preferably underneath the ad7643, or as close as possible to the ad7643. if the ad7643 is in a system where multiple devices require analog-to-digital ground connections, the connections should still be made at one point only, a star ground point, established as close as possible to the ad7643. to prevent coupling noise onto the die, avoid radiating noise, and reduce feedthrough: ? do not run digital lines under the device. ? run the analog ground plane under the ad7643. ? shield fast switching signals, like cnvst or clocks, with digital ground to avoid radiating noise to other sections of the board, and never run them near analog signal paths. ? avoid crossover of digital and analog signals. ? run traces on different but close layers of the board, at right angles to each other, to reduce the effect of feedthrough through the board. the power supply lines to the ad7643 should use as large a trace as possible to provide low impedance paths and reduce the effect of glitches on the power supply lines. good decoupling is also important to lower the impedance of the supplies presented to the ad7643, and to reduce the magnitude of the supply spikes. decoupling ceramic capacitors, typically 100 nf, should be placed on each of the power supplies pins, avdd, dvdd, and ovdd. the capacitors should be placed close to, and ideally right up against, these pins and their corresponding ground pins. additionally, low esr 10 f capacitors should be located in the vicinity of the adc to further reduce low frequency ripple. the dvdd supply of the ad7643 can be either a separate supply or come from the analog supply, avdd, or from the digital interface supply, ovdd. when the system digital supply is noisy, or fast switching digital signals are present, and no separate supply is available, it is recommended to connect the dvdd digital supply to the analog supply avdd through an rc filter, and to connect the system supply to the interface digital supply ovdd and the remaining digital circuitry. refer to figure 23 for an example of this configuration. when dvdd is powered from the system supply, it is useful to insert a bead to further reduce high frequency spikes. the ad7643 has four different ground pins: refgnd, agnd, dgnd, and ognd. refgnd senses the reference voltage and, because it carries pulsed currents, should have a low impedance return to the reference. agnd is the ground to which most internal adc analog signals are referenced; it must be connected with the least resistance to the analog ground plane. dgnd must be tied to the analog or digital ground plane depending on the configuration. ognd is connected to the digital system ground. the layout of the decoupling of the reference voltage is important. to minimize parasitic inductances, place the decoupling capacitor close to the adc and connect it with short, thick traces. evaluating the ad7643 performance a recommended layout for the ad7643 is outlined in the documentation of the eval-ad7643-cb evaluation board for the ad7643. the evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a pc via the eval- control brd3 .
ad7643 rev. 0 | page 28 of 28 outline dimensions compliant to jedec standards mo-220-vkkd-2 pin 1 indicator top view 6.75 bsc sq 7.00 bsc sq 1 48 12 13 37 36 24 25 5.25 5.10 sq 4.95 0.50 0.40 0.30 0.30 0.23 0.18 0.50 bsc 12 max 0.20 ref 0.80 max 0.65 typ 1.00 0.85 0.80 5.50 ref 0.05 max 0.02 nom 0.60 max 0.60 max pin 1 indicator coplanarity 0.08 seating plane 0.25 min exposed p a d (bottom view) paddle connected to agnd. this connection is not required to meet the electrical performances. figure 42. 48-lead lead frame chip scale package [lfcsp_vq] 7 mm 7 mm body, very thin quad (cp-48-1) dimensions shown in millimeters compliant to jedec standards ms-026-bbc top view (pins down) 1 12 13 25 24 36 37 48 0.27 0.22 0.17 0.50 bsc lead pitch 7.00 bsc sq 1.60 max 0.75 0.60 0.45 view a 9.00 bsc sq pin 1 0.20 0.09 1.45 1.40 1.35 0.08 max coplanarity view a rotated 90 ccw seating plane 7 3.5 0 0.15 0.05 figure 43. 48-lead low profile quad flat package [lqfp] (st-48) dimensions shown in millimeters ordering guide model temperature range package description package option ad7643bcpz 1 ?40c to +85c 48-lead lead frame chip scale package (lfcsp_vq) cp-48-1 ad7643bcpzrl 1 ?40c to +85c 48-lead lead frame chip scale package (lfcsp_vq) cp-48-1 ad7643bstz 1 ?40c to +85c 48-lead low profile quad flat package (lqfp) st-48 ad7643bstzrl 1 ?40c to +85c 48-lead low profile quad flat package (lqfp) st-48 eval-ad7643cb 2 evaluation board eval-control brd3 3 controller board t 1 z = pb-free part. 2 this board can be used as a standalone evaluation board or in conjunction with the eval-control brd3 for evaluation/demonstrat ion purposes. 3 this board allows a pc to control and communicate with all analog devices, inc. evaluation boards ending in the cb designators . ?2006 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d06024C0C4/06(0) ttt

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